1. Field of the Invention
This invention relates to a semiconductor device using a partial SOI substrate and a manufacturing method thereof and more particularly to a semiconductor device having elements respectively formed in an SOI region and non-SOI region of a partial SOI wafer in which the non-SOI region is formed by selectively removing portions of a BOX (Buried OXide) layer and silicon layer which are formed on partial regions of an SOI (Silicon On Insulator) substrate and a manufacturing method thereof.
2. Description of the Related Art
The structure having MOSFETs formed on an SOI substrate has a bright future for high-performance logic devices. However, it is known that a parasitic MOSFET or parasitic bipolar transistor is operated depending on the source-drain voltage condition due to the so-called substrate-floating effect when gate voltage which turns OFF the MOSFET is applied and a leakage current flows in the source-drain path. The above characteristic causes a problem of, for example, deterioration of retention for applications in which the specification for the leakage current is strict as in a memory cell transistor of the DRAM, for example, and is not preferable. Further, in the sense amplifier circuit of the DRAM, since the threshold voltages of the paired transistors are shifted due to the substrate-floating effect, the sense margin is lowered. Due to the above problems, it is difficult to form a DRAM with the same MOSFET structure as that of the high-performance logic circuit on the SOI substrate.
Further, demand for a device having the high-performance logic circuit and DRAM mounted together thereon is strong and it is desired to develop the technique for forming the DRAM together with the logic device whose performance is enhanced by use of the SOI structure.
For example, like a DRAM-mounted logic device (embedded DRAM; eDRAM), a partial SOI substrate having an SOI region and non-SOI region is effectively used for forming a circuit which requires both the SOI substrate and bulk substrate. As one of the manufacturing methods for forming the partial SOI substrate, a method for selectively etching and removing a silicon layer (which is referred to as an SOI layer) on a buried oxide layer (BOX layer) and the BOX layer on the SOI substrate and burying silicon in the etched-out region is considered.
FIGS. 1A to 1D are cross-sectional views showing the manufacturing steps of forming the partial SOI substrate, for illustrating a manufacturing method of the conventional semiconductor device. An SOI substrate 11 shown in FIG. 1A is formed by bonding a supporting substrate 12, BOX layer 13 and SOI layer 14 by use of the wafer bonding method or the like.
Next, as shown in FIG. 1B, the SOI layer 14 on the SOI substrate 11 is partially removed. Then, part of the BOX layer 13 which corresponds to the removed portion of the SOI layer 14 is removed to form an opening 15 and expose the surface of the supporting substrate 12 as shown in FIG. 1C.
After this, as shown in FIG. 1D, a silicon layer 16 is formed on the supporting substrate 12 in the opening 15 to form a non-SOI region.
If the partial SOI substrate is formed by use of the above method, the distance Δ1 from the surface 11A of the SOI substrate 11 to a formation interface 16A of the silicon layer 16 becomes almost equal to the sum Δ2 of the thicknesses of the SOI layer 12 and box layer 13 as shown in FIG. 2 and is approx. 0.3 to 0.6 μm in the present SOI substrate 11.
However, if transistors or trench type memory cells of a DRAM are formed in the non-SOI region formed by use of the above manufacturing method, the active region of the device crosses the formation interface 16A of the silicon layer 16 so as to significantly increase the leakage current and degrade the pause characteristic and a desired electrical characteristic cannot be attained.
FIG. 3 is a cross-sectional view of a trench type memory cell MC of a DRAM and shows leakage current paths. The memory cell MC is configured by a cell transistor CT and a cell capacitor (trench capacitor) CC. A gate electrode 23 is formed above part of the silicon layer 16 which lies between a source region 21 and a drain region 22 of the cell transistor CT with a gate insulating film 24 disposed therebetween. As shown in FIG. 3, the source region 21, drain region 22 and depletion layer 25 of the cell transistor CT cross the formation interface 16A of the silicon layer 16.
At the OFF time of the cell transistor CT, a leakage current Ioff flows between the source region 21 and the drain region 22. Further, a junction leakage current Ij flows through a junction between the source region 21 and the supporting substrate 12.
Thus, in the semiconductor device using the conventional partial SOI substrate and the manufacturing method thereof, the leakage current increases to a large extent and the pause characteristic is considerably degraded.